For managers and leads

SDLP is Techvify's stage-gated backbone for software delivery: 5 stages, 5 Quality Gates, from Initiation to Closeout. It applies to both Fixed-Price (PB) and ODC projects, and it runs in two lanes — a Standard Lane and an AI-Assisted Lane (ADLC) — chosen per stage at planning time and recorded in the Project Plan.

SDLP is not a way of working
Quoted from the source document: "SDLP is a stage-gate governance framework, NOT a lifecycle/execution model like Agile, Scrum, or Waterfall — teams choose their own execution methodology within each stage; the SDLP only fixes the objective and the Gate." That is why the two D3 runbooks sit underneath this page, not beside it: they describe how work actually runs inside these stages.
D3 practice
Before a project starts, the PM sits down with PQA and agrees the process for that specific project. Not every project applies the whole framework. What the two of them agree is recorded in the Project Plan, and that becomes the version of SDLP the project is audited against.
What the source document says
  • The lane is chosen per stage — Standard, AI-Assisted, or a mix of both — decided at planning time by DM/PM and documented in the Project Plan tailoring section.
  • Waived items are marked N/A with the reason recorded, and the tailoring is approved per the Process Tailoring guideline.
  • At a gate, any item not met needs a waiver approved by the DM before sign-off.
  • PQA is a service role, not present on every project by default. When PQA is not engaged, PM / Tech Lead / QA Lead perform the same checks themselves against the same criteria.

Every activity from the source workbook, side by side. Open a stage to see what each lane does, who is accountable, and what comes out.

1
Initiation
Scope and operating model established.
Charter & plan approved; requirements signed off; risks & environment ready.
Standard Lane
1Open the project and register it in the Project Archive Library (PAL).
PIC
PM (DM approves)
Input
DO / Estimation / Contract
Output
Standard Project Folder; PAL registration
Verify
PM confirms folder matches Standard Project Folder Structure template; PAL entry checked by DM
Process ref.
Opening & Closing Process (03-PCD.TVF.DMO.INT)
2Conduct the project kick-off meeting with key stakeholders and confirm the agenda.
PIC
PM, AM (DM approves)
Input
Kick-off agenda
Output
Kick-off Slide; signed Meeting Minutes
Verify
Minutes signed by DM; attendee list matches Project Plan stakeholders
Process ref.
Kick-Off Slide (11-TP.TVF.DMO_INT)
3Create the Project Plan, covering schedule, resources, communication, quality and budget, and establish the Risk Register.
PIC
PM (DM approves)
Input
Estimation, WBS, resources
Output
Project Plan; Risk Register (probability + mitigation)
Verify
DM reviews Plan against Estimation/WBS; Risk Register has >=5 items with mitigation
Process ref.
Project Plan (13-TP.TVF.DMO_INT) + Risk Management (11-TP.TVF.DMO_INT)
4Elicit the Business Requirements Document (BRD), obtain written sign-off, and initialize the security requirements.
PIC
BA, PM (Client approves)
Input
Customer needs
Output
BRD (written sign-off); Q&A File
Verify
Client/PM sign-off in writing; BA confirms Security Requirements section present
Process ref.
Business Requirements Document (02-TP.TVF.DMO_INT)
5Prepare the development environment and tooling by provisioning dev, test and staging infrastructure, and configuring IDEs, ticketing and internal tools.
PIC
DevOps, Tech Lead (PM approves)
Input
BRD (approved)
Output
Working dev/test environment; tool access granted for the team
Verify
Tech Lead confirms every team member can build and run the base project skeleton before Stage 2 begins
Process ref.
Not yet standardized in QMS v1.0
AI-Assisted Lane (ADLC)
1Open the project and register it in the Project Archive Library (PAL) — the same administrative step as the Standard lane, since it happens before any AI tooling is engaged.
PIC
PM (DM approves)
Input
DO / Estimation / Contract
Output
Standard Project Folder; PAL registration
Verify
PM confirms folder matches Standard Project Folder Structure template; PAL entry checked by DM
Process ref.
Opening & Closing Process (03-PCD.TVF.DMO.INT)
2Conduct the kick-off meeting together with the Standard lane team, confirming the AI-Assisted lane as one of the topics agreed at this meeting.
PIC
PM, AM (DM approves)
Input
Kick-off agenda
Output
Kick-off Slide; signed Meeting Minutes
Verify
Minutes signed by DM; attendee list matches Project Plan stakeholders
Process ref.
Kick-Off Slide (11-TP.TVF.DMO_INT)
3Let AI analyze historical project data to benchmark estimates and detect risk patterns, then draft a Project Plan for the PM to review.
PIC
PM (DM approves)
Input
Historical project data
Output
Project Plan (AI-assisted estimation + Risk forecast)
Verify
PM cross-checks AI-drafted benchmarks against actual similar past projects before accepting
Process ref.
See 05_ADLC Lane Reference (ad-hoc AI tooling, not a formal ADLC phase)
4Elicit the BRD and obtain written sign-off, then initialize the security requirements, using the same approach as the Standard lane.
PIC
BA, PM (Client approves)
Input
Customer needs
Output
BRD (written sign-off); Q&A File
Verify
Client/PM sign-off in writing; BA confirms Security Requirements section present
Process ref.
Business Requirements Document (02-TP.TVF.DMO_INT)
5Install the SpecKit toolkit, set up the project's constitution file defining its coding principles, capture the environment profile, and enable real-time security scanning in the IDE.
PIC
TL, SE
Input
BRD (approved)
Output
SpecKit scaffolding + constitution.md committed; environment profile captured; IDE SAST active
Verify
TL confirms constitution.md is reviewed and the team can run /speckit-* commands successfully end-to-end
Process ref.
See 05_ADLC Lane Reference - Stage Setup, Step (0) + DEPLOY setup (connect/env/ide-setup)
Gate 1 criteria — applies to both lanes
Kick-off minutes signed; Project Plan approved (incl. Quality Plan + budget); BRD written sign-off; Risk Register initialized; Security Requirements in BRD; dev/test environment ready.
2
Definition
What will be built is agreed and baselined.
Requirements baselined; scope committed in writing; backlog & test strategy set.
Standard Lane
1Elicit user and business requirements, then produce the User Requirements Document (URD) with all open questions resolved.
PIC
BA (PM approves)
Input
Approved BRD
Output
URD; Q&A File (resolved)
Verify
PM confirms all Q&A items resolved before URD finalized
Process ref.
RD Process [Gap Action #6] + URD Template [New]
2Translate the URD into the Software Requirements Specification (SRS), then have it reviewed and approved by the PM and the client.
PIC
BA (PM, Client approve)
Input
URD
Output
SRS (approved)
Verify
PM/Client review SRS against URD line-by-line; sign-off recorded
Process ref.
RD Process; SRS Template (01E-TP.TVF.DMO_SD)
3Create Figma mockups and prototypes to visualize the proposed design.
PIC
UI/UX (BA approves)
Input
BRD/URD
Output
Figma Design
Verify
BA reviews mockups against BRD business intent
Process ref.
Not yet standardized in QMS v1.0
4Build the Product Backlog with prioritized user stories and acceptance criteria, approved by the Product Owner.
PIC
BA, PM (PO approves)
Input
SRS
Output
Product Backlog (Jira/ADO)
Verify
PO confirms backlog items map 1:1 to SRS requirements
Process ref.
Product Backlog Template (05-TP.TVF.DMO_SD)
5Create the Test Plan with a defined pass-rate threshold, and build the Requirements Traceability Matrix (RTM).
PIC
QA Lead, QC (PM approves)
Input
SRS
Output
Test Plan; RTM
Verify
QA Lead confirms Test Plan covers all SRS requirements; RTM has no gaps
Process ref.
Testing process; Test Plan (03-TP.TVF.DMO_CT) + Traceability/RTM [New - Gap Action #1]
AI-Assisted Lane (ADLC)
1Elicit requirements and produce the URD with all questions resolved — the same human-led step used in the Standard lane, feeding the same URD into the AI-generated specification.
PIC
BA (PM approves)
Input
Approved BRD
Output
URD; Q&A File (resolved)
Verify
PM confirms all Q&A items resolved before URD finalized
Process ref.
RD Process [Gap Action #6] + URD Template [New]
2Create the Figma design with node IDs, design tokens, component states and responsive breakpoints, so it is fully machine-readable before the AI analysis stage begins.
PIC
UI/UX Designer (lead), BA (review)
Input
Approved BRD, User Stories, wireframe sketches
Output
Figma design (node IDs, all states, design tokens complete) [Mandatory]
Verify
BA confirms design matches business requirements. GATE (shared with Stage entry): BRD approved + Figma complete + User Stories on ADO/Jira with AC + constitution.md committed - ALL FOUR required before Pre-Plan Analysis.
Process ref.
See 05_ADLC Lane Reference - Stage (1) Input, Step (2)
3Let AI generate the specification document by reconciling the user story, the Figma design and prior analysis into structured user stories, testable acceptance criteria and functional requirements.
PIC
SE (AI-assisted), BA (review), PM (scope), PO (approve)
Input
User Story (ADO/Jira link), Figma design link, preplan.md
Output
spec.md (User Stories, BDD ACs, FR-xxx list) [Mandatory]
Verify
GATE - PO and BA must approve spec.md: AC correctly reflects business intent; all FR-xxx numbered and testable; scope confirmed by PM (no drift from BRD); PO sign-off recorded.
Process ref.
See 05_ADLC Lane Reference - Stage (3) Specify & Plan, Step (5)
4Confirm the Product Backlog directly from the specification document, ensuring every backlog item is linked to a specification artifact.
PIC
BA, PM (PO approves)
Input
spec.md
Output
Product Backlog linked to spec chain
Verify
PO confirms backlog items linked to spec.md artifacts, no orphan stories
Process ref.
Same as Standard (backlog process not ADLC-specific)
5Create the Test Plan and, optionally, let AI expand it into detailed test cases, tracing back to the specification instead of a separate traceability matrix.
PIC
QA Lead, SE (PM approves)
Input
spec.md
Output
Test Plan; test-cases.md (optional)
Verify
SE confirms test-cases.md traces to spec.md ACs via spec chain (commit history)
Process ref.
See 05_ADLC Lane Reference - optional /speckit-test-cases step
Gate 2 criteria — applies to both lanes
SRS approved; scope committed in writing; Q&A resolved; Product Backlog + Test Plan approved; traceability established (RTM).
3
Solution & Architecture
The solution is decided and made buildable.
Design & decisions approved; security reviewed; pipeline & work breakdown ready.
Standard Lane
1Design the High-Level Design (HLD) and the accompanying Architecture Decision Records (ADRs).
PIC
SA (DM/HOD, Client approve)
Input
SRS, Product Backlog
Output
HLD Document; ADR
Verify
DM/HOD + Client review HLD against SRS; ADRs reviewed for completeness (DAR criteria)
Process ref.
Software Design Process; Architecture Design (08-TP.TVF.DMO_SD) + DAR Process Document [New - Gap Action #39]
2Produce the Low-Level Design (LLD), including UML diagrams and API contracts.
PIC
Tech Lead, SA (Tech Lead approves)
Input
HLD
Output
LLD Document; UML; API Contracts
Verify
Tech Lead reviews LLD against HLD for consistency
Process ref.
Software Design Process; Detail Design (09-TP.TVF.DMO_SD)
3Conduct a Security Design Review following OWASP guidelines.
PIC
SA, Tech Lead (SA/TL approve)
Input
HLD, BRD security req.
Output
Security Design Review; ADR (security)
Verify
SA/Tech Lead confirm OWASP Top 10 checklist completed; threats documented in ADR
Process ref.
Security requirements & Threat model (08-TP.TVF.DMO_SD)
4Set up the CI/CD environments and define the team's coding conventions.
PIC
DevOps, Tech Lead (Tech Lead approves)
Input
HLD
Output
CI/CD Pipeline; Code Project Structure; Coding Convention
Verify
DevOps confirms pipeline runs build+test successfully end-to-end before Stage 4 begins
Process ref.
CM Process/GUI + Git Guideline [New - Gap Action #15]
5Decompose the HLD into a Technical Backlog, and produce the PI Plan and Integration Checklist.
PIC
Tech Lead, QA Lead (PM approves)
Input
HLD, LLD
Output
Tech Backlog; PI Plan + Integration Checklist
Verify
PM confirms Tech Backlog items map to HLD/LLD scope; PI Plan reviewed
Process ref.
PI Process/GUI [New - Gap Action #11] + Checklist PI [New - Gap Action #12]
AI-Assisted Lane (ADLC)
1Design the HLD and ADRs with AI support for anti-pattern review, while the Solution Architect retains ownership of the final architectural decision.
PIC
SA (DM/HOD, Client approve); AI as reviewer
Input
SRS, Product Backlog
Output
HLD Document; ADR
Verify
DM/HOD + Client review HLD against SRS; ADRs reviewed for completeness (DAR criteria)
Process ref.
Software Design Process; Architecture Design (08-TP.TVF.DMO_SD) + DAR Process Document [New - Gap Action #39]
2Let AI generate the technical plan once the specification is approved, covering the constitution compliance check, data model, API contracts and project structure.
PIC
SE, Tech Lead (Tech Lead approves)
Input
spec.md, preplan.md, constitution.md
Output
plan.md, data-model.md, contracts/ [Mandatory - same ADLC PLAN phase as spec.md]
Verify
GATE - TL must approve plan.md: Constitution compliance gate PASS; Clean Architecture correct; API contracts complete and match spec.md ACs.
Process ref.
See 05_ADLC Lane Reference - Stage (3) Specify & Plan, Step (6)
3Let AI break the technical plan down into an ordered task list, naming exactly what each task touches.
PIC
SE, PM (PM approves)
Input
plan.md, spec.md
Output
tasks.md [Mandatory - final artifact of the ADLC PLAN phase]
Verify
PM/SE review tasks.md for clarity - each task must be estimable, assignable, trackable
Process ref.
See 05_ADLC Lane Reference - Stage (3) Specify & Plan, Step (7)
4Note that translating the design into code happens later, as part of implementation in the Execution & Testing stage, not as a separate architecture-stage activity.
PIC
SE
Input
Approved screens (Figma/Stitch)
Output
N/A - see Stage 4 "Feature Development" row
Verify
N/A - verified as part of the Implementation stage code review checklist
Process ref.
See 05_ADLC Lane Reference - Stage (4) Implement, Step (9) (not a separate step here)
5Draft a threat model and testable security requirements from the specification before coding begins, keeping security a checkpoint in the pipeline rather than a review at the end.
PIC
threat-modeler agent (AI-driven); SA/Tech Lead review
Input
spec.md
Output
Threat model + security requirements
Verify
SAST pre-check results reviewed alongside manual OWASP checklist; STRIDE model reviewed by SA/Tech Lead before Stage 3 Gate.
Process ref.
See 05_ADLC Lane Reference - DEPLOY, Step (17)
6Set up the CI/CD environment as in the Standard lane, plus configure the repository-indexing tool that lets AI reason over the whole codebase once implementation begins in the next stage.
PIC
DevOps, Tech Lead (Tech Lead approves)
Input
HLD
Output
CI/CD Pipeline; Code Project Structure; Coding Convention; repo-indexing configured
Verify
Tech Lead confirms CI/CD pipeline is green end-to-end; confirms repo-indexing tool is configured and ready for Stage 4
Process ref.
See 05_ADLC Lane Reference - CI/CD pipeline config; repo-indexing runs meaningfully from Stage 4 onward
Gate 3 criteria — applies to both lanes
HLD/LLD approved; ADRs documented; CI/CD operational; PI Plan/Checklist completed; Tech Backlog ready.
4
Execution & Testing
Built and verified until fit to release.
Quality thresholds met; no critical defects open; release candidate verified.
Standard Lane
1Plan the iteration by defining its objective, completion criteria and task list.
PIC
PM, Tech Lead (PM approves)
Input
Product Backlog, Tech Backlog
Output
Iteration Plan
Verify
PM confirms Iteration Objective + completion criteria agreed by team before the iteration starts
Process ref.
Project Plan (13-TP.TVF.DMO_INT); WBS Schedule (06-TP.TVF.DMO_INT)
2Develop features through self-review, peer review and Tech Lead approval, with CI/CD running on every commit.
PIC
SE, Tech Lead (Tech Lead approves)
Input
LLD, coding convention
Output
Source Code; Code Review Checklist; CI/CD artifacts
Verify
Tech Lead approves PR after code review checklist completed
Process ref.
Secure Coding Process; Unit Test Review (01-CL.TVF.DMO_CT), Code Review (02-CL.TVF.DMO_CT)
3Execute unit, integration and regression testing per the Test Plan to reach a pass rate of at least 95%, and run performance and load testing against the defined thresholds.
PIC
QC, SE (QA Lead approves)
Input
Test Plan, Test Cases
Output
Test Report; Bug Report; Load/Stress Test Report
Verify
QA Lead confirms pass-rate >=95% before sign-off; confirms performance results meet defined latency/throughput targets with zero regressions
Process ref.
Testing process; Test Case & Test Report (04-TP.TVF.DMO_CT)
5Conduct the increment review and retrospective, then publish the Progress Report comparing planned versus actual effort and recording any corrective action.
PIC
PM (DM approves)
Input
Actual vs planned effort
Output
Weekly Report; Retro Report; Corrective Action log
Verify
DM reviews planned-vs-actual deviation; corrective action logged if overrun
Process ref.
Weekly Report (07-TP.TVF.DMO_CT)
AI-Assisted Lane (ADLC)
1Confirm the task list scope fits the iteration capacity before the iteration starts.
PIC
PM (confirms scope)
Input
tasks.md
Output
Iteration Plan (scope confirmed)
Verify
PM confirms tasks.md scope matches iteration capacity before it starts
Process ref.
Same ceremony as Standard; ADLC supplies tasks.md as input
2Review all approved artifacts, then let AI implement the code phase by phase from the task list, reading the design tokens from the earlier analysis, with security gates running on every commit.
PIC
SE (AI-assisted)
Input
tasks.md, preplan.md, plan.md, spec.md, constitution.md
Output
Production Code; Unit Tests; tasks.md updated
Verify
CODE REVIEW CHECKLIST (SE reviews each block): Clean Architecture; DDD; error handling pattern; i18n; design alignment; API contracts; AC coverage 100%. A NAMED engineer signs off - individual accountability, not sampling.
Process ref.
See 05_ADLC Lane Reference - Stage (4) Implement, Steps (8)(9)(10)
3Prepare the test environment, then let AI run the automated test pipeline end to end: inspecting the application, generating test scenarios and page objects, executing the full suite, and running load testing.
PIC
SE, QC (AI-assisted)
Input
Implemented feature, spec.md AC
Output
qa-report.md (BDD pass/fail, FR coverage map) [Mandatory]; Load/stress test report
Verify
QC reviews qa-report.md BDD coverage map against spec.md ACs; confirms performance results meet targets
Process ref.
See 05_ADLC Lane Reference - Stage (5) QA Testing, Steps (11)-(14)
4Have a named engineer review the AI-generated QA report and make the mandatory go or no-go decision before the pull request can proceed.
PIC
SE, QC (joint decision)
Input
qa-report.md
Output
QualityGatekeeper decision [MANDATORY]
Verify
MODE A (pass): review recommendations, confirm FR coverage 100%. MODE B (fail after 3 retries): fix / document known issue / TL-confirmed skip.
Process ref.
See 05_ADLC Lane Reference - Step (13), MANDATORY
5Conduct the increment review and retrospective, then publish the Progress Report — the same ceremony as the Standard lane, with an additional audit of AI artifact completeness where PQA is engaged.
PIC
PM (DM approves)
Input
Actual vs planned effort
Output
Weekly Report; Retro Report; Corrective Action log
Verify
DM reviews planned-vs-actual deviation; corrective action logged if overrun; if PQA engaged, PQA additionally audits completeness
Process ref.
Weekly Report (07-TP.TVF.DMO_CT)
Gate 4 criteria — applies to both lanes
Test pass rate >=95%; performance/load test meets defined thresholds; no open Critical/High bugs; code review + SAST clean.
5
Deployment & Closeout
Released, accepted and formally closed.
Release validated; client acceptance obtained; closure & lessons recorded.
Standard Lane
1Perform the Final Inspection (FI), a comprehensive pre-release check of the release candidate.
PIC
QA Lead, Tech Lead (PQA if engaged; PM approves)
Input
Release Candidate (Gate 4 passed)
Output
Final Inspection Report - PASS required before deploy
Verify
QA Lead + Tech Lead jointly confirm all 7 FI checklist items PASS; if PQA engaged, PQA independently verifies
Process ref.
Final Inspection Checklist (01-CL.TVF.DMO_RLSP)
2Prepare the Deployment Checklist, covering the go/no-go decision, backup plan and rollback trigger.
PIC
PM, DevOps (PM/Tech Lead approve)
Input
Release Candidate, UAT Plan
Output
Deployment Checklist; Go-no-go criteria
Verify
PM/Tech Lead confirm go-no-go criteria met; backup/recovery point confirmed
Process ref.
Release Process (PCD.TVF.DMO_RLSP)
3Deploy to production and monitor the system for 24 to 48 hours afterward.
PIC
DevOps, PM (PM approves)
Input
Deployment Checklist (approved)
Output
Deployed Software (Production)
Verify
DevOps confirms deployment succeeded; monitors 24-48h post-deploy for anomalies
Process ref.
Release Process (PCD.TVF.DMO_RLSP); Release Note (03-TP.TVF.DMO_RLSP)
4Support User Acceptance Testing (UAT) and any resulting hotfixes, then obtain the UAT sign-off.
PIC
PM, QA, Dev (Client approves)
Input
Deployed software, UAT Plan
Output
UAT Sign-off Document; Hotfix releases
Verify
Client confirms UAT Sign-off; all Critical/High defects resolved and retested
Process ref.
User Acceptance Testing Plan (05-TP.TVF.DMO_CT) / Report (06-TP.TVF.DMO_CT)
5Prepare the Quality Report and handover materials, conduct the post-mortem, and record the Lesson Learned before archiving in the QMS.
PIC
PM, Team (DM approves)
Input
Full project history
Output
Closure Report; Lesson Learned; CSS; QMS Archive
Verify
DM reviews Closure Report + Lesson Learned before approving project closure
Process ref.
Lesson Learnt (05-TP.TVF.DMO_TERM); CSS Analysis Report (02-TP.TVF.DMO_TERM); Post-mortem meeting Slide (06-TP.TVF.DMO_TERM)
AI-Assisted Lane (ADLC)
1Perform the Final Inspection, the same comprehensive pre-release check used in the Standard lane, since it validates the release itself rather than how it was built.
PIC
QA Lead, Tech Lead (PQA if engaged; PM approves)
Input
Release Candidate (Gate 4 passed)
Output
Final Inspection Report - PASS required before deploy
Verify
QA Lead + Tech Lead jointly confirm all 7 FI checklist items PASS; if PQA engaged, PQA independently verifies
Process ref.
Final Inspection Checklist (01-CL.TVF.DMO_RLSP)
2Prepare the Deployment Checklist as in the Standard lane, with AI log monitoring configured and production promotion gated through an automated release pipeline that always starts in a lower environment first.
PIC
PM, DevOps (PM/Tech Lead approve)
Input
Release Candidate, UAT Plan
Output
Deployment Checklist; Go-no-go criteria; AI log monitoring configured
Verify
Additionally confirm AI log monitoring configured and tested; confirm production sync is gated behind manual approval
Process ref.
See 05_ADLC Lane Reference - DEPLOY, Step (17)
3Promote to production automatically through the CI/CD release pipeline, with AI monitoring logs for anomalies.
PIC
DevOps
Input
Deployment Checklist (approved)
Output
Deployed Software (automated CI/CD pipeline)
Verify
AI anomaly detection alerts reviewed alongside manual monitoring; Security + Tech Lead sign-off confirmed present before considering deploy complete
Process ref.
See 05_ADLC Lane Reference - DEPLOY, Step (17)
4Support User Acceptance Testing and any hotfixes, then obtain sign-off — the same process as the Standard lane, since UAT validates business behavior regardless of which lane built the release.
PIC
PM, QA, Dev (Client approves)
Input
Deployed software, UAT Plan
Output
UAT Sign-off Document; Hotfix releases
Verify
Client confirms UAT Sign-off; all Critical/High defects resolved and retested
Process ref.
User Acceptance Testing Plan (05-TP.TVF.DMO_CT) / Report (06-TP.TVF.DMO_CT)
5Let AI draft the Lesson Learned from tickets, commits and the QA report for human review, and automatically score how closely delivery followed the process, feeding any gaps back into the next project cycle.
PIC
PM, SE (PM approves)
Input
Tickets, commits, qa-report.md, delivery telemetry
Output
Lesson Learned (AI-synthesized, human-verified); Method scorecard; backlog items for next cycle
Verify
PM/team reviews AI-synthesized draft for accuracy; confirms adherence gaps are converted into concrete backlog items
Process ref.
See 05_ADLC Lane Reference - OPERATE, Step (18)
Gate 5 criteria — applies to both lanes
FI (Final Inspection) passed; UAT signed off; go-no-go + backup/recovery + rollback trigger + post-deploy monitoring met; Acceptance Note signed; CSS + Lesson Learned + QMS archive complete.

This is the acceptance criteria list a project is signed off against. Every item must be Required-and-Met, or carry a waiver approved by the DM, before the gate is passed. Open a gate to see its criteria.

Generic criteria — apply at every gate
  • G1Have the objectives / exit criteria of this stage been completely satisfied AND approved by the appropriate person (not just completed)?
  • G2Are all work products of this stage completed, reviewed, and stored per the QMS artifact convention?
  • G3Does the NEXT stage's plan (process, resource, effort, schedule, quality) provide sufficient assurance of good-quality output?
  • G4Is the quality of inputs being handed to the NEXT stage good enough to ensure good-quality work product there?
Legend✓required in that lane–not applicableRTM req.required, but through a different artifact
1
Initiation Sign-off
7 criteria Std 7/7 AI 7/7
#GroupCriterionStdAIVerifierEvidence
1GovernanceKick-off meeting conducted; minutes signed and archivedStandard✓AI lane✓DM/PMMinutes document
2PlanningProject Plan approved by DM (schedule, resource, Quality Plan, budget, tailoring lane)Standard✓AI lane✓DMProject Plan
3RequirementsBRD approved - written sign-off (verbal not acceptable)Standard✓AI lane✓PM/ClientSigned BRD
4RiskRisk Register initialized (>=5 risks, mitigation + probability)Standard✓AI lane✓PMRisk Register
5SecuritySecurity requirements section in BRDStandard✓AI lane✓BABRD section
6ToolingProject Folder created; project registered in PALStandard✓AI lane✓PMFolder + PAL
7TimingGate completed within 7 working days from Actual Start DateStandard✓AI lane✓PMTimeline
2
Definition Sign-off
10 criteria Std 6/10 AI 8/10
#GroupCriterionStdAIVerifierEvidence
1RequirementsSRS approved by PM + Client - written sign-offStandard✓AI lane–spec.mdPM/ClientSigned SRS
2Requirementsspec.md approved by PO/BA [AI lane]Standard–AI lane✓PO/BAspec.md in repo
3RequirementsScope formally committed in writingStandard✓AI lane✓PMWritten commitment
4RequirementsAll Q&A items resolved - zero blocking questionsStandard✓AI lane✓BAQ&A File
5AI Artifactspreplan.md committed to repoStandard–AI lane✓SERepo: preplan.md
6AI Artifactsspec.md + checklists/requirements.md committedStandard–AI lane✓SERepo: spec.md
7BacklogProduct Backlog created (User Stories + AC) in Jira/ADOStandard✓AI lane✓PMJira/ADO
8TestingTest Plan approved with pass-rate threshold definedStandard✓AI lane✓QA LeadTest Plan
9TraceabilityTraceable BRD->SRS->Test Cases [Std: RTM / AI: spec chain]StandardRTM req.AI laneSpec chain req.BA/QC/PQARTM or repo
10SecuritySecurity NFRs included in SRS/spec.mdStandard✓AI lane✓BASRS/spec.md
3
Architecture Sign-off
10 criteria Std 8/10 AI 9/10
#GroupCriterionStdAIVerifierEvidence
1DesignHLD approved by DM/HOD + ClientStandard✓AI lane✓DM/HODHLD document
2DesignLLD approved by Tech LeadStandard✓AI lane✓Tech LeadLLD document
3DesignADRs documented for key decisionsStandard✓AI lane✓SA/TLADR document
4AI Artifactsplan.md reviewed (Constitution Check = PASS) [AI lane]Standard–AI lane✓Tech Leadplan.md in repo
5AI Artifactstasks.md reviewed by PM/SE [AI lane]Standard–AI lane✓PM/SEtasks.md in repo
6SecuritySecurity design review completed; threats in ADRStandard✓AI lane✓SA/TLADR (security)
7InfrastructureCI/CD pipeline operationalStandard✓AI lane✓DevOpsPipeline demo
8InfrastructureCoding convention publishedStandard✓AI lane✓Tech LeadConvention doc
9IntegrationPI Plan + integration checklist completedStandard✓AI lane–Tech LeadPI Plan
10PlanningTech Backlog / tasks.md ready for the first iterationStandard✓AI lane✓PMBacklog/tasks.md
4
Code Freeze & Alpha/Beta Sign-off
11 criteria Std 9/11 AI 11/11
#GroupCriterionStdAIVerifierEvidence
1QualityAll Iteration Objectives met - completion criteria (Definition of Done or equivalent) verifiedStandard✓AI lane✓PMIteration/progress reports
2QualityTest pass rate >= 95% regression; performance/load test meets defined thresholds, 0 regressionsStandard✓AI lane✓QCTest Report
3QualityNo open Critical/High bugs at Code FreezeStandard✓AI lane✓QC/PMBug tracker
4CodeCode Review completed on all PRsStandard✓AI lane✓Tech LeadPR history
5CodeSAST clean - SonarQube Quality Gate PASSStandard✓AI lane✓DevOps/TLSonarQube report
6AI ArtifactsAll 5 mandatory artifacts in PR presentStandard–AI lane✓PQAPR artifacts
7AI ArtifactsQualityGatekeeper review completedStandard–AI lane✓SE/QCqa-report.md
8TestingDAST test completed in STGStandard✓AI lane✓QC/DevOpsDAST Report
9BuildRelease Candidate deployed to STG; smoke test passedStandard✓AI lane✓DevOpsSTG deployment
10ReportingPlanned-vs-actual reported, overruns resolvedStandard✓AI lane✓PMWeekly Report
11Sign-offPM + Tech Lead both sign off Code FreezeStandard✓AI lane✓PM/TLSign-off doc
5
UAT Sign-off & Project Closure
13 criteria Std 13/13 AI 13/13
#GroupCriterionStdAIVerifierEvidence
1UATUAT completed and signed off by ClientStandard✓AI lane✓Client/PMUAT Sign-off
2UATCritical/High UAT defects resolved and re-testedStandard✓AI lane✓QC/PMBug tracker
3DeploymentGo-no-go criteria metStandard✓AI lane✓PM/TLChecklist
4DeploymentBackup/recovery point confirmedStandard✓AI lane✓DevOpsBackup log
5DeploymentPost-deploy monitoring >= 24hStandard✓AI lane✓DevOpsMonitoring log
6DeploymentRollback trigger defined and team briefedStandard✓AI lane✓PM/DevOpsRunbook
7SecurityFinal DAST scan before go-liveStandard✓AI lane✓DevOps/QCDAST report
8HandoverAcceptance Note signed by ClientStandard✓AI lane✓Client/PMAcceptance Note
9HandoverUser Manual + Installation Guide deliveredStandard✓AI lane✓BAHandover package
10ClosureCSS submittedStandard✓AI lane✓PMCSS record
11ClosureLesson Learned documented (structured)Standard✓AI lane✓PMLesson Learned
12ClosureArtifacts uploaded to QMS/PAL with metadataStandard✓AI lane✓PM/PQAPAL/QMS
13ClosureClosure Report approved by DMStandard✓AI lane✓DMClosure Report
Final Inspection — pre-release product check
7 criteria Std 7/7 AI 0/7
PQA performs this if the PQA service is engaged on the project; otherwise QA Lead + Tech Lead self-check. FI is distinct from PCV: PCV audits whether the team followed the process, FI inspects whether the product itself is ready for release.
#GroupCriterionStdAIVerifierEvidence
1CodeCode freeze confirmed - no changes to Release Candidate since Gate 4Standard✓AI lane·Tech LeadGit tag / release record
2TestingAll test results (Unit/Integration/System/Regression) documented and archivedStandard✓AI lane·QCTest Report
3DocumentationUser Manual, Installation Guide, and Release Note finalizedStandard✓AI lane·BAHandover package
4SecuritySAST/DAST results clean - no unresolved Critical/High vulnerabilitiesStandard✓AI lane·DevOps/QCScan report
5ComplianceLicense / IP compliance verified - no unauthorized dependenciesStandard✓AI lane·Tech LeadDependency audit
6Build IntegrityDeployment package matches signed-off Release Candidate (version/checksum)Standard✓AI lane·DevOpsBuild manifest
7RollbackRollback plan tested and confirmed readyStandard✓AI lane·DevOpsRollback runbook

Per feature, from the ADLC guideline. A pull request missing one of these fails the PQA audit.

preplan.mdMandatory
Figma node inventory, UI analysis per screen, mismatch report, resolved PO Q&A, implementation directives.
spec.mdMandatory
User Stories, Acceptance Criteria (BDD), FR-xxx requirements, non-functional requirements.
plan.mdMandatory
Constitution PASS gate, data model, API contracts (OpenAPI YAML), project file structure.
tasks.mdMandatory
Atomic task breakdown, phased, dependency-ordered, effort estimated. Input to /speckit-implement.
qa-report.mdMandatory
BDD pass/fail per test scenario, FR coverage map, root cause analysis, QualityGatekeeper decision.
BRDMandatory
Business Requirement Document: scope, business use cases, rules, ACs, risks, stakeholder list.
Figma DesignMandatory
UI/UX mockup with node IDs, design tokens, component states, and responsive breakpoints.
Production CodeMandatory
Frontend (Vue 3/TS) + Backend (.NET Clean Architecture) + database migrations.
E2E Test FilesMandatory
Playwright BDD test suite: Gherkin .feature files + Page Object TypeScript classes.
API Contracts (OpenAPI)Mandatory
OpenAPI specifications for all new or modified endpoints introduced by the feature.
research.mdMandatory
Technology decisions, library evaluations for Phase 0 Research.
Change Request DocConditional
Formal scope change record per Change Request Process.
constitution.mdConditional
Project-specific engineering principles and non-negotiable coding rules.
PR descriptionMandatory
Pull Request summary: artifact checklist, QA summary, Constitution compliance, test coverage overview.
Delivery Manager (DM)
Approve Project Plan, Charter, Architecture, and Closure. Governance oversight of all stage-gate decisions. Escalation point for risks and issues.
Project Manager (PM)
Own Project Plan, schedule, Risk Register, Quality Plan, budget, communication. Track planned-vs-actual effort with corrective action. Gate sign-off coordination. Weekly reporting.
Business Analyst (BA)
Analyze and document requirements (URD, BRD, SRS). Review spec.md for business intent [AI lane]. Maintain traceability. Obtain formal written scope sign-off.
Solution Architecture (SA)
Design HLD and lead Architecture Decision Records. Review AI-assisted architecture analysis; owns final architecture decisions.
Technical Leader (TL)
Review plan.md for architecture/DDD/API contracts [AI lane]. Set up constitution.md [AI lane]. Approve Pull Requests. Sign-off on Code Freeze. Co-owns FI (Final Inspection) with QA Lead before production deployment at Stage 5.
Software Engineer (Developer) (SE)
Execute SpecKit workflow commands [AI lane]. Review EVERY AI-generated code block. Perform QualityGatekeeper review before PR creation [AI lane]. Own all engineering decisions.
Quality Control (QC)
Execute Unit/Integration/System/Regression testing per pass-rate threshold. Review qa-report.md and validate QualityGatekeeper decisions [AI lane].
DevOps (DevOps)
Set up CI/CD; configure SAST/DAST tools; execute production deployments; own backup/recovery and rollback procedures.
AI Engineer (AI Engineer)
Develop and maintain AI-powered applications; support AI tooling configuration for ADLC-adopting projects.
UI/UX Designer (UI/UX)
Prepare Figma mockups with node IDs, design tokens, component states. Ensure Figma is ready before /speckit-preplan [AI lane].
Comtor (Comtor)
Interpret in client meetings; translate documents and technical materials.
Product Owner (PO)
Define product vision; manage Product Backlog; approve BRD/spec.md before technical planning; validate delivered features during UAT.
Bridge Software Engineer (BrSE)
Understand and analyze requirements from clients; bridge communication between client and delivery team.
Process Quality Assurance (PQA)
PQA is a SERVICE role, not present on every project by default - engaged per project agreement. When engaged: conducts Process Compliance Verification (PCV) at stage boundaries via the 6-step Quality Gate Review (tailor checklist, audit OK/NOK/N/A, evaluate performance, summarize, report, follow up Findings), audits mandatory artifacts and QualityGatekeeper completion [AI lane], and performs Final Inspection (FI) at Stage 5. See 04_Quality Gate Checklist for full workflow. When PQA is NOT engaged, these checks are self-performed by PM/Tech Lead/QA Lead using the same Gate criteria.
Account Manager (AM)
Engage customers on needs/expectations; facilitate commercial discussions; present at Kick-off.
Technical Consultant (Tech Consultant)
Analyze, consult, and propose technical solutions for complex or specialized engagements.

R = Responsible · A = Accountable · C = Consulted · I = Informed

Activity / DeliverableStage PM DM BA TL SE QC PQA PO DevOps
Project Charter & PlanS1RAC---I--
BRD (Business Requirement Doc)S1CIR---IA-
Risk RegisterS1RAC---I--
URD + SRS / spec.mdS2CIRCC-IA-
Figma DesignS2RIRCIIIA-
Test PlanS2/3CICC-RI--
preplan.md / spec.md [AI]S2IIC-R-IA-
HLD + LLD + ADRS3CAIRC-I--
plan.md + tasks.md [AI]S3CI-AR-I--
constitution.md [AI]S3II-RC-I--
CI/CD Pipeline SetupS3II-AC-I-R
Iteration Plan (each iteration)S4RIIRIII--
Source Code + PRS4II-ARCI--
Test Case + Test ReportS4II-CCRI--
qa-report.md + QualityGatekeeper [AI]S4II-CRRI--
Weekly Report (planned-vs-actual)S4RI-IIIC--
PQA Artifact Audit [AI] (if PQA service engaged)S4II-ICCR--
FI - Final Inspection (pre-release) [PQA Service - if engaged]S5AI-RIRC-I
Deployment Checklist + Go-liveS5RA-CCII-R
UAT SupportS5RACCCRIA-
Quality ReportS5AIICIRC--
Lesson Learned + QMS ArchiveS5RACCCCC--
Customer Satisfaction SurveyS5RAI---I--
Stage Gate Sign-offs (all)AllRACCICI--

SDLP fixes the objective and the gate. These two runbooks describe the execution model D3 uses inside them.

Source: SDLP_v1.1.xlsx — QMS, Techvify Delivery. This page reproduces that workbook; the workbook remains the source of truth.